1. Field of the Invention
The present invention relates to an analog-to-digital (A/D) converter having an improved reference voltage generation unit for generating reference voltages that is, for example, particularly suited to a multi-bit delta-sigma A/D converter used in wireless receivers requiring a high signal-to-noise ratio (SNR).
2. Description of Related Art
While the present invention can be adapted to a common discrete-time A/D converter, the case of a delta-sigma A/D converter will be described below as an example.
Converting analog signals to digital signals facilitates signal transmission and processing and improves efficiency. Accordingly, A/D converters perform an important function in wireless receivers used in mobile telephones and the like. An increase in data rates following the recent implementation of broadband in communication systems has also made it necessary to realize wideband and high SNRs as well as low power consumption in A/D converters. This has led to the use of delta-sigma A/D converters, originally used in measuring instruments and the like, with respect to which high SNRs are readily realized.
Generally, a delta-sigma A/D converter having higher-order filter characteristics is used to realize a high SNR. Since closed loop gain in the feedback loop configuration of a delta-sigma A/D converter increases with higher-order filter characteristics, adversely affecting stability, stability is ensured by using a multi-bit configuration to suppress the amount of instantaneous fluctuation. A multi-bit configuration is effective with high SNRS, since quantization noise can be reduced.
FIG. 9 is a block diagram showing an exemplary conventional n-th order delta-sigma A/D converter. This n-th order delta-sigma A/D converter has a closed loop configuration composed of an n-th order integrator 30, a quantizer 31, and a digital-to-analog (D/A) converter 32. The n-th order integrator 30 is composed of integrators 33[0] to 33[n], subtractors 34[0] to 34[n], input circuits 35[0] to 35[n], and feedback circuits 36[0] to 36[n]. The digital output of the quantizer 31 is converted to an analog value by the D/A converter 32, and supplied to the subtractors 34[0] to 34[n] via the feedback circuits 36[0] to 36[n]. The differences between the output signals of the input circuits 35[0] to 35[n] and the output signals of the feedback circuits 36[0] to 36[n] are obtained by the subtractors 34[0] to 34[n], and the output signals therefrom are input respectively to the integrators 33[0] to 33[n]. 
With the configuration in FIG. 9, reference voltages of the quantizer 31 are supplied using a reference voltage generation unit 37 having a configuration such as shown in FIG. 10, for example, in order to realize a multi-bit configuration. If the maximum input voltage range of the quantizer 31 is assumed to be ±VFS, an m-bit quantizer requires 2m−1 decision values, with the voltage interval of the decision values being 2×VFS/(2m−1). Increasing the bit count of the multi-bit configuration twofold in order to improve stability and the SNR therefore means that the intervals between the decision values need to be narrowed by substantially half each. This leads to an increase in the decision error rate due to dispersion in the decision values, making it impossible to maintain high conversion accuracy (linearity).
Since the dispersion accuracy of the resistors is generally significant at around 5%, particularly in the case where the reference voltages are generated by voltage division using resistors R1 to Rm+1 connected in series, as shown in FIG. 11, high conversion accuracy cannot be maintained, resulting in an increase in quantization error.
For example, assume that the VFS is ±0.25V, and 3-bit decision values are (± 6/7, ± 4/7, ± 2/7, 0)×VFS. In this case, the decision value dispersion of the higher decision values will be 6/7×VFS×5%=0.02V, with respect to a decision value interval of 2/7×VFS=0.07V, meaning that the decision values vary across approximately one third of the decision value interval. Further, with 5-bit decision values, the decision value interval will be 0.016V, resulting in the quantizer not operating properly because of the decision value dispersion being greater than the decision value interval.
This shows that in order to maintain high conversion accuracy (linearity) and increase the bit count of a multi-bit configuration, it is important to reduce dispersion in decision values as much as possible.
Methods proposed to solve this problem involve correcting the multi-bit decision values to obtain high conversion accuracy (linearity) (e.g., see FIG. 1 of JP 5-152967A).
FIG. 12 is a block diagram showing the outline of a delta-sigma A/D converter having a configuration for correcting multi-bit decision values. Two delta-sigma A/D converters 40a and 40b are used, each of which is respectively composed of subtractors 41a and 41b, integrators 42a and 42b, quantizers 43a and 43b and D/A converters 44a and 44b. A signal obtained by subtracting the output signal of the integrator 42a of the delta-sigma A/D converter 40a from an analog input signal with a subtractor 45 is supplied to the subtractor 41b of the other delta-sigma A/D converters 40b. The quantization error signal produced by the quantizer 43a of the delta-sigma A/D converter 40a is thereby measured by the other delta-sigma A/D converter 40b. The quantization error signal can be reduced by generating a correction signal based on this measurement result so as to cancel the quantization error signal, and adding the generated correction signal with an adder 46 on the output side.
However, with the delta-sigma A/D converter shown in FIG. 12, a high precision delta-sigma A/D converter needs to be added as a correction circuit, increasing the circuitry size and making an increase in power consumption inevitable.